Cache coherence

Results: 102



#Item
51Assessment of Cache Coherence Protocols in Shared-memory Multiprocessors by  Alexander Grbic

Assessment of Cache Coherence Protocols in Shared-memory Multiprocessors by Alexander Grbic

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Source URL: www.eecg.toronto.edu

Language: English - Date: 2003-09-25 20:16:55
52SCORPIO: 36-Core Shared Memory Processor Demonstrating Snoopy Coherence on a Mesh Interconnect Chia-Hsin Owen Chen Collaborators: Sunghyun Park, Suvinay Subramanian, Tushar Krishna, Bhavya Daya, Woo Cheol Kwon, Brett Wil

SCORPIO: 36-Core Shared Memory Processor Demonstrating Snoopy Coherence on a Mesh Interconnect Chia-Hsin Owen Chen Collaborators: Sunghyun Park, Suvinay Subramanian, Tushar Krishna, Bhavya Daya, Woo Cheol Kwon, Brett Wil

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Source URL: www.hotchips.org

Language: English - Date: 2014-07-19 19:25:26
53Microsoft Word - OCMJMX_091007_FINAL.rtf

Microsoft Word - OCMJMX_091007_FINAL.rtf

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Source URL: www.sl.com

Language: English - Date: 2012-09-20 16:07:53
54The NUMAchine Multiprocessor: Design and Analysis Robin Grindley  A thesis submitted in conformity with the requirements

The NUMAchine Multiprocessor: Design and Analysis Robin Grindley A thesis submitted in conformity with the requirements

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Source URL: www.eecg.toronto.edu

Language: English - Date: 1999-11-29 17:16:53
55Design and Implementation of the NUMAchine Multiprocessor A. Grbic, S. Brown, S. Caranci, R. Grindley, M. Gusat, G. Lemieux, K. Loveless, N. Manjikian , S. Srbljic , M. Stumm, Z. Vranesic and Z. Zilic   

Design and Implementation of the NUMAchine Multiprocessor A. Grbic, S. Brown, S. Caranci, R. Grindley, M. Gusat, G. Lemieux, K. Loveless, N. Manjikian , S. Srbljic , M. Stumm, Z. Vranesic and Z. Zilic  

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Source URL: www.eecg.toronto.edu

Language: English - Date: 1999-09-21 22:20:54
56The NUMAchine Multiprocessor R. Grindley, T. Abdelrahman, S. Brown, S. Caranci, D. DeVries, B. Gamsa, A. Grbic, M. Gusat, R. Ho, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, P. McHardy, S. Srbljic, M. Stumm, Z. Vra

The NUMAchine Multiprocessor R. Grindley, T. Abdelrahman, S. Brown, S. Caranci, D. DeVries, B. Gamsa, A. Grbic, M. Gusat, R. Ho, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, P. McHardy, S. Srbljic, M. Stumm, Z. Vra

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Source URL: www.eecg.toronto.edu

Language: English - Date: 2000-09-02 04:07:38
57Detecting and Alerting on Fault Conditions in an Oracle Coherence Distributed Caching System Thomas Lubinski SL Corporation Corte Madera, CA

Detecting and Alerting on Fault Conditions in an Oracle Coherence Distributed Caching System Thomas Lubinski SL Corporation Corte Madera, CA

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Source URL: www.sl.com

Language: English - Date: 2012-09-20 16:07:55
58Design Trade-Offs in High-Throughput Coherence Controllers Anthony-Trung Nguyen Microprocessor Research Labs Intel Corporation Santa Clara, CA[removed]removed]

Design Trade-Offs in High-Throughput Coherence Controllers Anthony-Trung Nguyen Microprocessor Research Labs Intel Corporation Santa Clara, CA[removed]removed]

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Source URL: iacoma.cs.uiuc.edu

Language: English - Date: 2003-09-30 19:13:24
59ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment∗ Xuehai Qian, Wonsun Ahn, and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Abstract

ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment∗ Xuehai Qian, Wonsun Ahn, and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Abstract

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Source URL: iacoma.cs.uiuc.edu

Language: English - Date: 2010-09-19 14:00:08
60ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Envionment Xuehai Qian, Wonsun Ahn, Josep Torrellas University of Illinois

ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Envionment Xuehai Qian, Wonsun Ahn, Josep Torrellas University of Illinois

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Source URL: iacoma.cs.uiuc.edu

Language: English - Date: 2010-12-23 23:00:55